发布日期: 2024年07月23日 22:21

姓名：殷鹏

政治面貌：中共党员

电子邮箱：yinpeng@henu.edu.cn

殷鹏，男，中共党员，博士。主要研究方向：高速数据传输接口、信号处理等数模混合集成电路设计。

202206-至今 河南大学物理与电子学院 讲师

河南省自然科学基金青年项目 主持

第七届（2023）全国大学生集成电路创新创业大赛 华中赛区三等奖 优秀指导教师

Peng Yin, Honeli Chen, Yingjun Xia et al., High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 11, pp. 5166-5177, Nov. 2024.

Peng Yin, Zhou Shu, et al. A Low-area and Low-power Comma Detection and Word Alignment Circuits for JESD204B/C Controller. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2925 2935, Jul. 2021.

Qiushi Wang, Peng Yin*, N. Wu, et al. A High-Logic-Density, Low-Power Control Character Detection and Identification Circuit for the JESD204B Data Link Layer. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 4, pp. 1600-1604, April 2023.

Jun Deng, Peng Yin*, Xin Lei, et al. A Tunable Parameter, High Linearity Time to Digital Converter Implemented in 28 nm FPGA. IEEE Transactions on Instrumentation & Measurement, vol. 70, pp. 1-12, 2021.

Peng Yin, Yingjun Xia, et al. A Low-area Low-power Column-parallel Digital Decimation Filter Using 1-bit Pre-BWI Topology for CMOS Image Sensor in 40-nm CMOS Process. Circuits, Systems and Signal Processing 41, pp. 2681-2698, 2022.

Shalin Huang, Mingdong Li, Huan Li, Peng Yin, et al. A Sub-1 ppm/°C Bandgap Voltage Reference With High-Order Temperature Compensation in 0.18-μm CMOS Process, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, pp. 1408-1416, April 2022.

Yingjun Xia, Zhou Shu, Tianmei Shen, Peng Yin, et al. A 10 GHz Low Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS /PI Based CDR. IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12, pp. 5432 5442, Dec. 2020.

Zhou Shu, Shalin Huang, Zhipeng Li, Peng Yin, et al. A 5 13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40 nm CMOS Process. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 10, pp. 3378 3388, Oct. 2020.